`timescale 1ns/1ns
module Tff_2(
           input wire data, clk, rst,
           output reg q
       );
reg data_r;
always@(posedge clk or negedge rst)
	begin
		if (!rst)
			data_r <= 1'b0;
		else
			data_r <= (data & ~data_r) | (~data & data_r);
	end
always@(posedge clk or negedge rst)
	begin
		if (!rst)
			q <= 1'b0;
		else
			q <= (data_r & ~q) | (~data_r & q);
	end

endmodule
